A semiconductor memory device may include arrays of memory cells. Each memory cell may include a transistor having an electrically floating body in which an amount of electrical charge is stored. The amount of electrical charge stored in the electrically floating body may represent a logic high (i.e., a binary “1” data state) or a logic low (i.e., a binary “0” data state). The amount of electrical charge stored in the electrically floating body may decay with time, and thus it may be necessary to restore the amount of electrical charge in the electrically floating body.
Various techniques may be employed to refresh a semiconductor memory device. In one technique, a data state may be read from and/or written back to a memory cell of the semiconductor memory device by applying suitable control signals. For example, current sense amplifier circuitry may be employed to read a data state of a memory cell. The current sense amplifier circuitry may compare a memory cell current with a reference current, such as for example, the current of a reference cell. The data state of the memory cell, for example, a logic high (i.e., a binary “1” data state) or a logic low (i.e., a binary “0” data state), may be determined based at least in part on the comparison between the memory cell current and the reference current.
After determining the data state of the memory cell, suitable control signals may be applied the memory cell in order to write back the determined data state. The suitable control signals employed for reading and/or writing back the data state may consume large amount of power. Also, the current sense amplifier circuitry employed to read and/or write back the data state may occupy large amount of space.
In addition, the current sense amplifier circuitry may sequentially address each row of memory cells to perform read and write operations. Typically, a refreshing process (e.g., reading and/or writing back a data state) may require 10 to 50 nanoseconds for each row and, depending on a number of rows in the semiconductor memory device, the refreshing process for the entire semiconductor memory device may require 10 to 50 milliseconds. Therefore, the refresh time period may limit the capacity of the semiconductor memory device.
Also, pulsing between positive and negative gate biases during current read and write operations may reduce a net quantity of charge carriers stored in an electrically floating body region of a memory cell within the semiconductor memory device, which, in turn, may gradually eliminate data stored in the memory cell. In the event that a negative voltage is applied to a gate of a memory cell transistor, thereby causing a negative gate bias, a channel of minority charge carriers beneath the gate may be eliminated. However, some of the minority charge carriers may remain “trapped” in interface defects. Some of the trapped minority charge carriers may recombine with majority charge carriers, which may be attracted to the gate, and net majority charge carriers located in the electrically floating body region may decrease over time. This phenomenon may be characterized as charge pumping, which is a problem because the net quantity of charge carriers may be reduced in the memory cell, which, in turn, may gradually eliminate data stored in the memory cell.
In view of the foregoing, it may be understood that there are significant problems and shortcomings associated with current techniques for refreshing semiconductor memory devices.